A material just one atomic layer thick has worked across 224 measured transistors on a two-inch wafer. The devices carried the positive charges needed for the p-type half of complementary electronics—a side of atom-thin chip design that has lagged behind its electron-carrying partner. But this is still a materials test, not a finished circuit or production chip. University of Tokyo research announcement Nature paper
The result comes from a Nature paper published online September 30, 2026. The University of Tokyo says the devices came from three growth batches and were tested across wafer locations. That account is the researchers’ report, not an independent replication. Wafer-scale epitaxy growth of high-mobility p-type boron carbon nitride High-performance p-type 2D semiconductor realized at wafer scale
A film designed to carry holes
The material is boron carbon nitride, or BCN: a single layer grown continuously across the two-inch substrate. The reported process controls two molecular precursors so carbon enters the boron-nitride lattice rather than forming separate clumps. Microscopy and the authors’ structural interpretation indicate that carbon atoms and pairs mainly occupy nitrogen sites. Wafer-scale epitaxy growth of high-mobility p-type boron carbon nitride High-performance p-type 2D semiconductor realized at wafer scale
The team reports a bandgap near 1.90 electronvolts, hole mobility around 100 square centimetres per volt-second, and an on/off current ratio around 10^8. The reported test structures used one-micrometre channels, five-micrometre widths and a 20-nanometre hafnium-oxide gate dielectric. These are measured laboratory device results, not evidence of faster phones, lower power use or commercial performance. Wafer-scale epitaxy growth of high-mobility p-type boron carbon nitride High-performance p-type 2D semiconductor realized at wafer scale
The missing partner is still essential
A practical complementary circuit needs both p-type hole transport and n-type electron transport. BCN could fill the p-type role, but the team still identifies carbon-composition control, low-temperature growth and integration with complementary circuits as unresolved problems. Contacts, device variation, manufacturability and reliability are also necessary tests beyond an isolated transistor result. High-performance p-type 2D semiconductor realized at wafer scale p-Type 2D transistors from contact physics to complementary integration
The race has already reached larger wafers
BCN is not the first large-wafer 2D transistor integration. In June 2026, imec, ASML and TSMC reported combining other 2D materials for n- and p-type transistors on a 300-millimetre wafer. Their collaborators reported 94 percent operational devices and a 50-nanometre contacted poly pitch; those claims concern different materials and process conditions, so they are not a direct BCN comparison. ASML, TSMC and imec bring industry-ready 2D-material transistors closer with breakthrough 300mm integration
What would make this future real?
Over the next five years, BCN could become a candidate for stacked or complementary 2D circuits if researchers can scale the growth process, control carbon placement and contacts, and pair it with an n-type device without losing performance. That is a scenario, not a launch forecast. It would weaken if independent tests fail to reproduce the mobility and uniformity, if the processing temperature conflicts with chipmaking, or if competing p-type materials prove easier to manufacture. The useful checkpoint is October 2027, when replication and early integration work should make the direction clearer.
The lasting test is whether the material’s chemistry, contacts and device uniformity survive the move from individual structures to coordinated circuits. BCN has cleared one important step by producing many measured p-type devices on a continuous film. The next question is whether it can reach industry-relevant wafer sizes and work beside n-type devices without losing its laboratory performance. University of Tokyo research announcement Review of p-type 2D transistor integration
